1. Field of the Invention
The present invention relates to a semiconductor device and method of forming the same. More particularly, the present invention relates to a semiconductor device having a gate contact structure capable of reducing interfacial resistance and a method of forming the same.
2. Description of the Related Art
The line width of patterns composing a semiconductor device constitute an important parameter which determines an integration density of the semiconductor device. In order to increase the integration density of the semiconductor device, the line width of the patterns may be decreased to a level corresponding to an increase of the integration density. However, with conductive patterns such as gate electrodes and interconnections, the line width decrease results in an electric resistance increase which leads to resistive capacitive (RC) delay. Conventional gate electrodes may be made of a silicon-based conductive material, e.g., n+ polysilicon and/or silicide having high specific resistance, etc. Technical problems due to the line width decrease become more serious for the gate electrode than the interconnections made of metallic material.
Metal gate technologies have been proposed for forming the gate electrodes with a metallic material having low specific resistance. One of these suggested technologies for forming the gate electrodes may utilize tungsten gate (W-gate) technology, where the specific resistance may be about 5.5×10−8 Ωm. Compared to this, the specific resistance of tungsten silicide (WSix) may be about 3×10−7 Ωm to 7×10−7 Ωm, and the specific resistance of n+ polysilicon may be about 10−5 Ωm. Notwithstanding the low specific resistance of tungsten, if the tungsten comes in direct contact with a gate insulating layer, technical problems such as degradation of reliability of the gate insulating layer may occur.
Therefore, when using the tungsten-gate, as illustrated in FIG. 1, a polysilicon layer 30 and a barrier metal layer 40 may be sequentially stacked between a tungsten layer 50 and a gate insulating layer 20 over a substrate 10. Impurity regions 25 may define source/drain regions. The barrier metal layer 40 may serve to prevent interfacial reaction and inter-diffusion between the polysilicon layer 30 and the tungsten layer 50. Metal nitride, e.g., tungsten nitride (WN) and/or titanium nitride (TiN), may be used for the barrier metal layer 40.
However, when the barrier metal layer 40 made of metal nitride is in contact with the polysilicon layer 30, an electrical contact resistance between them may appear to violate Ohm's Law. Specifically, the contact resistance may be larger compared with when an ohmic contact layer is used. This increase of contact resistance causes various technical problems.
For example, as shown in FIG. 2, an increase of interfacial contact resistance due to non-ohmic contact results in a signal delay of the circuit forming an inverter. The signal delay decreases the width of pulses L0 . . . Ln generated in the latch circuits LCH0 . . . LCHn, which constitute a page buffer of a FLASH memory. Therefore, a width of a generating pulse may be shorter than a length required in the nth latch circuit, and thus the FLASH memory may not operate normally. These technical problems may be commonly found in most general metal gate structures having a polysilicon layer. Nonetheless, due to pitting of active region, it is difficult to overcome these technical problems by the methods suggested by related art technologies.
More specifically, the gate structure may be electrically connected to the interconnection 70 by using a gate contact plug 60. In addition, impurity regions 15 may be formed on both sides of the gate structures, and the impurity regions 15 may be electrically connected to the interconnection 70 by using source/drain contact plugs 65. Contact holes for the gate contact plug 60 and source/drain contact plugs 65 may be formed simultaneously. Accordingly, the tungsten layer 50 and the barrier metal layer 40 may be further etched by a sum of their width (D), such that the gate contact plug 60 may be connected with the polysilicon layer 30. However, this additional etching may cause an excessive-etching of the impurity regions 15 (i.e. active-fitting). Therefore, although the gate contact plug 60 is in direct contact the tungsten layer 50, it becomes difficult to connect to the polysilicon layer 30.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention, and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.